Mémoire Online: Étude et modélisation du transistor GCGS DG MOSFET nanométrique

♣ Sommaire

List of figures
List of tables
List of publications
INTRODUCTION
CHAPTER I: DEEP SUBMICRON MOSFETs
I.1 – Introduction
I.2 – Evolution of CMOS technology
I.3 – MOSFET structure and operation
I.3.1. Presentation of the Structure
I.3.2. Operation Modes
I.4 – Small signal parameters
I.5 – Miniaturization effects
I.6 – Emergent solutions
I.6.1. High-k and metal gate integration
I.6.2. Strain-enhanced mobility
I.6.3. Multi-gate devices
I.7 – Nanotechnologies
I.8 – Conclusion
CHAPTER II :DEFECTS IN MOSFET DEVICES
II.1 – Introduction
II.2 – Defects classification
II.2.1 Bulk defects
II.2.2 Hot carrier
II.3 – Device degradation models
II.4 – Conclusion
CHAPTER III: MODELING OF GCGS DG MOSFET IN SUBTHRESHOLD REGION
III.1 – Introduction
III.2 – Model formulation
III.2.1. Surface potential
III.2.2.Threshold voltage
III.2.3. Subthreshold current
III.2.4. Subthreshold swing
III.3 – Results and discussion
III.4 – Conclusion
CHAPTER IV: MODELING OF GS DG MOSFET IN LINEAR AND SATURATION REGION
IV.1 – Introduction
IV.2 – Description of the studied structure
IV.3 – Proposed models formulation
IV.3.1. Piece-Wise Drain Current Models
IV.3.2. Surface potential based drain current model
IV.4 – Results and discussion
IV.4.1. Piece-Wise Drain Current Models
IV.4.2. Surface potential based drain current model
IV.5 – Impact of hot-carrier degradation on IC design
IV.6 – Conclusions
CONCLUSION AND FUTURE WORK
REFERENCES

♣ Extrait du mémoire

Chapter I: DEEP SUBMICRON MOSFETS
Abstract: The compact modeling of MOS transistors for integrated circuit design has, for many years, been driven by the needs of digital circuit simulation. Conventional bulk CMOS technology is still prevalent in the microelectronics industry. According to the International Technology Roadmap for Semiconductors, bulk MOS transistors will still be used for the 45 nm technology node (gate length around 18 nm), which is expected to be running by 2010.
The feasibility of 15 nm conventional MOS transistors in bulk CMOS technology has already been demonstrated.
The purpose of this chapter is to provide both an overview about the evolution of MOSFETs devices in addition to the basic physics theory required to build compact models required later for the deduction of some mandatory parameters and for the incorporation of new constraints in the function of the device.
I.1. INTRODUCTION
Since the 60’s the shrinking of electronic components has been driven by the fabrication of integrated circuits, which will continue for at least the next two decades. The critical feature size of the elementary devices (physical gate length of the transistors) will drop from 25 nm in 2007 (65 nm technology node) to 5 nm in 2020 (14 nm technology node). In the sub-10 nm range, beyond–CMOS (complementary MOS) devices will certainly play an important role and could be integrated on CMOS platforms in order to pursue integration down to nm structures. Si will remain the main semiconductor material in a foreseeable future, but the needed performance improvements for the end of the ITRS (international technology roadmap for semiconductors) will lead to a substantial enlargement of the number of materials, technologies and device architectures.
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