RT simulation offers several advantages to speed up the development of new product. One of these advantages being the possibility to test and develop controllers when the hardware is not yet available. This is a serious advantage in the case of high order multilevel converter, like MMC topology. When considering building a full-size converter, its physical size could raises serious issues for most laboratories, without even mentioning the cost to build such a complex structure. Simulation can also be useful to analyse the interaction between several MMC and conventional HVDC systems installed on the same power grid. Furthermore, it can perform factory acceptance test of the controller before its installation in the field. Nowadays, real-time simulator (RTS) are often used simply to accelerate simulations, as several hours of simulation can be required to run a few seconds simulation, for a power grid having two or three converter stations using conventional single processor simulation software. This chapter introduces fundaments of RT simulation; its advantages and constrains. Using these fundaments, RT simulation of an MMC will be undertaken. This topology was first introduced in (Lesnicar and Marquardt, 2003b), it is made of many identical sub-modules (SM) connected in series. Its modularity makes it suitable for various applications from medium voltage in a drive system, using only a few SM (Hiller et al., 2009), to large HVDC transmission system containing a wide range of SM (Rajasekar and Gupta, 2012; Peralta et al., 2012a). Connecting many of these SM in series reduces the voltage level that each sustains, decreasing the price of each component, reducing the switching losses, and smaller dV/dt at its AC bus, while producing a sinusoidal waveform with a very low total harmonic distortion (THD) eliminating the use of bulky reactive component filter.

This topology was first tested in large scale by ABB in 1997. It consisted in a 10 km overhead transmission line with a 3MW capability at ±10kV between Hällsjön and Grängesberg in Sweden. It was used as proof of concept and established the capability of this new topology. The MMC, was named HVDC light by ABB, and was first used in a commercial project in Australia between Mullumbimby and Bungalora. Its voltage rating was ±80kV with a power rating of 180MW commissioned in 2000. Not long after, Siemens commercialised a similar topology as HVDC PLUS. Its first commercial project was a submarine HVDC link connecting San Francisco city center to a substation in the Pittsburgh area, it was commissioned in 2010 (Zhang et al., 2012).

As of today, MMC projects being built are point-to-point converters only. Though actual HVDC network have been discussed theoretically, protection system for such network still need to be developed. ABB announced in November 2012 that they achieved a HVDC breaker called hybrid HVDC breaker(Callavik et al., 2012). Now that it has been used in a point-topoint setup, it will be tested in HVDC grid and should soon be commercialized. These new developments could change the future of power transportation.

Constraint introduced by RT simulation of power electronics converter in general

Until now, big differences still exist between what can be achieved with standard, or offline simulation software, and RTS. The major constrain is in the time available to solve the differential equations of power electronic circuit. Offline simulation usually uses variable-step solver which works as follow. For every simulation time-step, two solutions are found using two different orders of discretization; one higher than the other. The solver iterates, reducing the time-step at every iteration, until the difference between the two solutions is within a pre-set tolerance (Hartley et al., 1994). This process is very efficient for typical simulation of system with few disturbances. However, it becomes very slow in power electronic application, where stiff system with repetitive switching of semi-conductor needs to be solved. RT simulation, on the other hand, uses several processors, operating in parallel, with fixed-step solver, and uses a fix period of time to solve the differential equations. If a time-step of 50μs is chosen to discretize a system, the RTS has to solve the differential equations within that period. Larger model, with more state-space equations will naturally take more time to be solved; in this case there are very few solutions to obtain acceptable results. One can increase the chosen simulation time step, risking instability or inaccuracy. Having a more power full RTS allows to compute larger system. Computing power of RTS has increased exponentially over the last decade following Moore’s law (Schaller, 1997), and are suited to simulate relatively small model. However, the RT simulation of very large power system requires to decouple the system in smaller subsystems that can be solved in parallel (Baracos et al., 2001; Abourida et al., 2002). Nowadays most RTS achieves time step between 10μs to 50μs when using general-purpose processors, and between 100ns to 1μs when using field gate programmable array (FPGA).