The worldwide growth in data usage is continuing and accelerating even more with the emerging of new technologies such as 5th generation (5G) of mobile networks, ultra-high-speed fiber for internet, TV broadcasting of 4K contents and sensor networks. Therefore, the demand for more data and more bandwidth will continue to rise. In addition, the development of communication systems and the number of accessible services on the devices operating at millimeter-wave frequencies, make it necessary to develop low-cost and high-density integrated circuits and packages while retaining their performance. To accommodate this trend, cost-effective multi layer packaging technologies that offer high reliability with very good performance to maintain signal integrity are needed. These technologies must facilitate the size reduction for high-density packages. One of the main challenges in multi-layer structures is connecting different layers vertically through vias and enabling multi chip assemblies with interconnections that are as short as and as dense as possible.
Traditionally, the use of vertical interposers on silicon-based substrates and Through Silicon Vias (TSVs) to interconnect different layers has been one of the enabling technologies to allow high-density multi-chip integration, albeit with limited functionality and relatively high cost of fabrication. TSVs are filled by conductors such as copper, tungsten or polycrystalline silicon and they must have an isolation layer enclosing the conductive material to electrically isolated the silicon substrate and the TSV. This thin isolation layer does not work appropriately at high frequencies (Jonghyun Cho, 2010) and will also increase the DC loss of the system. In fact, despite the promising performance of TSVs and silicon interposers at low frequencies, the low resistivity of the silicon substrate leads to an excessive attenuation of transmitted signal at higher frequencies and particularly at millimeter wave frequencies. This high substrate loss will become a significant barrier to having an acceptable RF performance and to the development of 3D System in Package (SiP) application based on silicon. Moreover, the high loss of signals in TSVs produces a high noise coupling coefficient among different signals of the system and therefore it could increase jitter, phase noise of clock signals and the bit-errorrate in the data transmission of RF systems (Helmy & Ismail, 2006). In addition, the integration of RF passive components in the inner layer of silicon multi-layer structure is challenging. This challenge makes the design more complex and increases the number of fabrication steps, which consequently increases the cost of manufacturing. Finally, one should also note that the costly part in the silicon interposer manufacturing is via fabrication, isolation and filling. Therefore, finding a technological solution that can provide similar integration capabilities of silicon interposers with TSVs while addressing its limitations is the key problem to be addressed in this thesis.
A LTCC technology-based interposer is one possible alternative to silicon interposers. Indeed, LTCC technology provides the possibility of having an arbitrary number of dielectric layers using very low loss materials with high conductivity metals such as silver (Ag) and gold (Au). It is a promising technology for the realization of 3D integrated circuits and is well suited for packaging. However, the achievable pitch, size of vias, line width and line-to-line spacing with conventional LTCC fabrication methods are not comparable to those that can be achieved with silicon interposers with TSVs. Therefore, for LTCC-based interposers to be viable, the problems related to the standard LTCC fabrication process must be addressed and solutions must be proposed and developed.
In current telecommunication systems, due in part to the arrival of 5G technology and the Internet of Things (IoT), higher data speeds and greater bandwidth are required. The peak data rate for a whole system was around 100 Mbps in the late 1990s. By 2017 it had increased to more than 200 Gbps (C. Doerr, 2017). This need for higher speed of data transmission accelerates the need for new technologies and methods of data transfer to reach the desired rates and beyond. Therefore, this has served as a motivation for designers to move towards higher frequency bands such as millimeter-wave or optical frequencies (M. A. Jezzini, 2016).
This increasing of the speed of transmission will increase the losses in microwave circuits and systems. On one hand, in millimeter-wave and optical frequencies, the physical length of components and circuits are much smaller compared to the wavelength. On the other hand, demand for low cost and high reliable technology maintain performance of the system, makes it inevitable to move towards a new technology of fabrication and 3D packaging. In this project, a cost-effective technical method for this purpose based on Low Temperature Co-fired Ceramic (LTCC) technology is proposed and demonstrated.
Through Silicon Via (TSV)
In multi-layer circuits or packages based on silicon substrates, TSVs (Through Silicon Vias) are used to create a vertical transition path for the signals between different layers. This technique is an alternative to connection through bonding wires in order to increase the number of I/O, decrease signal delay and therefore increasing the speed of data transmission.
The silicon interposer has complicated fabrication process that increases the cost of manufacturing. In general, the costliest part is creating the hole via on the silicon substrate, isolation and filling. Fabricating this vertical electrical connection in a silicon substrate can be carried out by different techniques that require several steps. In one of these techniques, the first step is deep silicon etching where the holes are created on the silicon substrate. The next step is via oxide deposition to insulate the conductor from substrate to degrade the DC (Direct Current) loss of the substrate. After that, conductor plating is performed where a liquid conductor is injected into the hole. The processes of BEOL (Back End Of Line) Chemical Mechanical Polishing (CMP) or polishing the surface of wafer is the last step (Gong, 2014).
The silicon technology has some drawbacks at high frequency such as low resistivity for the TSV, ineffective isolation layer and high noise coupling coefficient among different signals due to the high value of signal loss. The resistivity of silicon substrate attenuates the signal passing vertically through TSV, and consequently this lossy signal degrades the RF performance at high frequencies (Soon Wee Ho, 2008). When current flows in the fine TSV, it can generate ohmic heat and accordingly hot spots in high-power chips, that negatively effect on the performance of the package (Heng Yun Zhang, 2014).
Additionally, the thin isolation layer surrounding the conductive material filled inside the TSV cannot prevent sufficiently the electrical parasitic coupling and critical substrate noise in the vicinity of active devices and/or adjacent TSVs. The effect of this noise is increasing the jitter and phase noise of clock signals as well as increasing the Bit-Error-Rate (BER) of the RF signals (Jonghyun Cho, 2010). In (Nauman H. Khan, 2011), coaxial TSVs with a diameter of 35.4 µm were used in order to overcome the noise issues of regular TSVs. In (Heng Yun Zhang, 2014), the TSVs with 10 µm diameter were used in high power circuits where two dummy dies and a thermal die were added to the circuit to improve the thermal performance of the structure.
The word Interposer comes from a Latin origin “interpōnere” which means, “to put up between” . An interposer electrically connects different parts of an electronic circuit through multiple layers and vias. In modern packaging technology, vertical interposers with flip chip attachments are used as an alternative to wire-bond connections. Generally, the performance of wire-bonds at frequencies above 30 GHz is not practical because it will have some impact on the performance of the device (C. Doerr, 2017). Due to the high characteristic impedance of wire-bonds, it would have an inductor behavior at high frequencies or behave as an antenna or a resonator (Rida, 2013). Therefore, wire bonding decreases the quality of the RF signals at high frequencies. The interposers are employed as a good alternative for wire-bonds in 3D packages; and most interposers in use today are made with silicon substrates and TSVs.
The use of silicon interposers is principally in the integration of Micro Electro Mechanical Systems (MEMS), Field Programmable Gate Array (FPGA) technologies, ASICs (Application Specific Integrated Circuits), server CPUs (Central Processing Unit), GPU (Graphics Processing Unit) and wireless devices (Timothy G. Lenihan, 2013).
In (Yan Yang, 2019), a CPW (Co-Planar Waveguide) transmission line on a silicon substrate in multilayer structure is presented where the Ground-Signal-Ground (GSG) TSV used for vertical interconnection. This structure operates in the frequency up to 40 GHz. The designed parameters of this transmission line such as via diameter, depth of via and center-to center pitch of the lines are 20 µm, 100 µm and 100 µm, respectively. The (Kuili Ren, 2016) presents a development process of thick silicon interposer for integrated inductor, micro-strip and CPW transmission lines. In their paper, a TSV with the diameter of 80 µm and the thickness of 300 µm for vertical interposer is reported. In other work presented on (J-R. Tenailleau, 2013), a TSV developed for the RF interposer applications with the nominal diameter of 75 µm and pitch of 125 µm, which is scalable for industrial production. They tested this via on a structure of dual via chain including CPW transmission line access, which is operates in the frequency range of DC to 20 GHz. In (Liyi Li, 2015) a via with a diameter of 28 µm, a pitch size of 80 µm and a depth of 162 µm was fabricated on silicon substrate by using Metal-assisted Chemical Etching (MaCE).